1. Field of the Invention
The present invention relates to interface circuits. In particular, the present invention relates to designing low noise programmable output buffers in interface circuits.
2. Discussion of the Related Art
FIG. 1 illustrates a typical communication system 100, which includes a device 110 communicating with a second device 120 over a signal path 130. Device 110 drives onto signal path 130 a data signal, which is received into device 120 by an input buffer 122. Typically, the propagation delay on signal path 130 depends on the drive strength of output buffer 112, the length of signal path 130, and the load on signal path 130 resulting from devices coupled to signal path 130, such as device 120. Typically, increasing the drive strength of output buffer 112 decreases the propagation delay on signal path 130. This technique is used frequently in the prior art (see, e.g., U.S. Pat. No. 4,779,013 to Tanaka).
In many situations, however, output buffer 112 is not specifically designed for use with device 110. Thus, a mismatch can seriously affect the performance of system 100. For instance, if output buffer 112 has a high drive strength but signal path 130 is only lightly loaded, noise can be introduced into device 120 through input buffer 122. FIG. 2 provides an example of a waveform 200 resulting from a overly strong output buffer driving a digital signal onto a lightly loaded signal path. Portion 215 of the waveform 200 represents, in a rising edge transition, the overshoot and brief oscillation ("ringing") resulting from this mismatch. Similar ringing characteristics are exhibited in a falling edge transition in portion 225 of waveform 200. The rapid switching of currents in buffer 112 can also lead to ground bounce and high frequency noises and high power dissipation, all of which are undesirable.